Semiconductor memory

ABSTRACT

A semiconductor memory comprising a plurality of memory cells, each cell including a pair of two-emitter transistors each having the collector connected to the base of the other transistor in the pair, one emitter connected to like emitter of the other transistor and to a common emitter bias terminal through an impedance element, and the other emitter connected to a corresponding one of bit drive lines in pair. The collectors of the transistors in pair are connected through respective switched impedance elements to a common collector voltage terminal, the respective switched impedance elements offering a small impedance when the collector voltage is at a high level and a large impedance when the collector voltage is at a low level.

United States Patent [191 Taniguchi et al.

in] 3,821,719 1 'June 28, 1974 [63] Continuation of Ser. No. 151,222, June 9, 1971,

abandoned.

[30] Foreign Application PriorityData June 12, 1970 Japan 45-50256 [52] US. Cl 340/173 FF, 307/238, 307/291, 307/299 A, 340/173 CP [51] Int. Cl.... H03k 3/286, G1 1c ll/4.0, G1 1c 7/00 [58] Field of Search 340/173 FF, 173 CP; 307/238, 289, 291, 299 A [56] References Cited UNITED STATES PATENTS I 3,389,383 6/1968 Burke 340/173 FF- 3,467,952 9/1969- ShiraishiQ 340/173 FF 3,505,573 4/1970 Wiedmann 340/173 FF 3,537,078 10/1970 'Pomeranz 340/173 FF 3,541,531 11/1970 Iwersen 340/173 FF 3,618,046 1l/l971 Bryant 340/173 FF 3,626,390 12/1971 Chang 340/173 FF 3,636,377 1/1972 Ecenomopoulos 340/173 FF OTHER PUBLICATIONS Wiedmann, Monolithic Circuit with Pinch Resistor,

2/71, IBM Technical Disclosure Bulletin, Vol. 13, No. 9, p. 2,469.

Gardner, Storage Cell, 11 /66, IBM Technical Disclosure Bulletin, Vol. 9, No. 6, p. 702.

S. Wiedmann, Monolithic Memory Cell with Junction FET Loads, 7/70, IBM Technical Disclosure Bulletin, Vol. 13, No. 2,1 11 477 478.

Gaensslen, FET Memory Cell Using Schottky Diodes as Load Devices, 7/70, IBM Technical Disclosure Bulletin, pp. 302-303, Vol. 13, No. 2.

Primary Examinr-Bemard Konick Assistant ExaminerStuart N. Hecker Attorney, Agent, or Firm-Craig and Antonelli 7 ABSTRACT A semiconductor memory comprising a plurality of memory cells, each cell includinga pair of two-emitter transistors each having the collector connected to the base of the other transistor in the pair, one emitter connected to like emitter of the other transistor and to a common emitter bias terminal through an impedance element, and the other emitter connected to a corresponding oneof bit drive lines in pair. The 001- pedance elements offering a small impedance when the collector voltage is at a high level and a large impedance when the collector voltage is at a low level.

8 Claims, 11 Drawing Figures 1 SEMICONDUCTOR MEMORY This application is a continuation of application Ser. No. 151,222, filed June 9, 1971, now abandoned.

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to semiconductor memories and, more particularly, to improvements of a memory cell employing two transistors each having a plurality of emitters.-

2. Description of the Prior Art The memory cell employing two multi-emitter transistors occupies extremely small area in an integrated circuit, so that it is suitable for organizing a semiconductor memory having a large capacity.

However, in the typical prior-art multi-emitter transistor memory cell, the resistance of the collector load is designed to be constant. Therefore, an intentto increase the speed of memory operation by increasing the cell current 1,, in a memory cell when it is in selected state results in increased cell current I in nonselected state, thus increasing the power consumption.

In a typical static MOS memory cell, the current ratio I /I can be increased by so arranging as to switch the load impedance of the cell between values for the selected state and non-selected state. With this type of memory cells, it has been possible to achieve low power consumption and a comparatively high operation speed of memory. i

It has also been proposed to increase the current ratio I /I of the memory cell consisting of two multiemitter transistors by switching the collector load resistance of the cell between values for the selected state and non-selected state of the cell. This proposal, however, requires impressing an address pulse on at least the common emitter terminal of the memory cell. Therefore, in the'selected state of the memory cell, at least one of the paired emitters connected to respective bit lines must carry current. This is a disadvantage in that it is impossible to sufficiently reduce power consumption in the circuit associated to a matrix arrangement organized with these memory cells, as will be described hereinafter in connection with FIG. 10 of the accompanying drawing.

In some of the prior-art memory cells of the kind mentioned above, address pulse is also applied to the collector terminals in order to provide low collector impedance of the cell when the address pulse is impressed on the common emitter terminal. This, however, requires a complicated circuit associated to the memory cell matrix because of two drive points for each memory cell.

SUMMARY OF THE INVENTION The present invention provides a novel bipolar type memory cell which can obviate the above drawbacks.

It is an object of the invention to provide a semiconductor memory comprising one or more memory cells each of which is selected by applying an address pulse to the collectors thereof so as to operate at a high speed with low power consumption.

The memory cell according to the invention essentially consists of two multi-emitter transistors each having a base, a collector connected to the base of the other transistor respectively and to a collector voltage source through a switched impedance element, two or BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a circuit diagram illustrating the principles underlying the invention.

FIGS. 2a and 2b show voltage waveforms and current waveforms illustrating the operation of the circuit of FIG. 1.

FIGS. 3 and 4 are schematics showing other fundamental circuit constructions than'that of FIG. 1.

FIGS. 5 to .9 show part of different embodiments of the invention.

FIG. 10 is a circuit diagram showing another embodiment of the invention.

DESCRIPTION O THE PREFERRED 1 EMBODIMENTS FIG. 1 shows the principles underlying the invention. Referring to the Figure, reference character M generally designates a memory cell employing'two multiemitter transistors T, and T each of which is illustrated to have two-emitters as an example. The'collectors of the transistors T, and T are connected torespective switched impedance elements Z and Zbzas loads. The collector of each of the transistors T, and T is connected tothe base of the other transistor. The transistors T, and T, have respective first emitters connected to each other and to an emitter bias terminal E, through an impedance element Z and respective second emitters connected to respective write/read amplifiers which are generally indicated as S, and S and will be described hereinafter. The second emittersare also connected to like second emitters of a plurality of transistors forming other memory cells in a matrix not shown.

The write/read amplifier S, comprises two transistors T and T having their emitters commonly connected to the second emitter of the multi-emitter transistor T, of the memory cell M and to an emitter bias terminal B, through a resistor R for determining the read current in the memory cell M. Likewise, the write/read amplifier S comprises two transistors T and T having their emitters commonly connected to the second emitter of the multi-emitter transistor T of the memory cell M and to an emitter bias terminal E through a resistor R for determining the read current in the memory cell M. The transistors T and T have their respective collectors connected through respective resistors R to respective collector bias terminals C and C Output terminals 0, and O, are also connected to the collectors of the transistors T andT A reference voltage V is impressed on the bases B, and B, of the transistors T and T Input signals V and V carrying information to be written-in are impressed on the bases 8;, and B of the transistors T, and T The transistors T and T have their respective collectors connected to respective collector bias terminals C and C which 3 may or may not be commonly connected to the terminals C and C FIG. 2 illustrates the operation of the construction described above. The emitter bias voltage V is made constant as shown in FIG. 2a. For the selective driving of the memory cell, the collector voltage V is made to assume a low level during the non-selected state S of thememory cell and a high level during the. selected state S, of the cell. During the non-selected state S,,, the collector voltages V and V on the transistors T and T (V V when the transistor T carries current) are lower than the reference voltage V applied to the write/read amplifier transistor bases B and B Thus, in this state no current flows through the second emitter of the transistor 2, so that current flowing through the resistor R in the write/read amplifier S is constituted by the current through the resistor R and transistor T alone, and the output voltage V appearing at the output terminal at the collector of the transistor T assumes a low level given as 7 Your ac 01 es an the output terminal 0 at the collector of the transistor T assumes a low level. v v

When the memory cell M is set in its selected state 8,, that is, when the voltage veg at the terminal C is switched to a high level, no current flows through terminal 1 since the collector voltage V on the transistor T is lower'than the reference voltage V but the collector voltage V on the transistor T becomes higher than the reference voltage V causing current 1,, to pass through terminal 2. The current I thus caused is substantially equal to the difference between the collec'tor current I and emitter current 1,; in the transistor T As this current I flows through the resistor R the current through the resistor R is reduced to increase the output voltage V at the output terminal 0 As a result, an information 1 is read out. On the other hand, since the transistor-T remains cut off, the output voltage V at the output terminal 0 of the amplifier 8, remains at.a low level with change in the collector voltage V In the non-selected state 8,, of the memory cell, the switched impedance elements Z and Z offer high impedances (including the case Z 2 to restrict the collector current I to an extremely low level, thus minimizing power consumption. On the other hand, in

the selected state S, the impedance of the switched impedance elements Z and Z is low, so that the level of the read current I is made very high. Thus, the memory cell can provide for a high speed ofmemory operation. Generally, the switched impedance elements Z and Z may offer'different impedances when the memory cell holds information stored, that is, when the memory cell is receiving a source voltage. Since the impedance of the switched impedance elements Z and Z5 is reduced upon selection of the memory cell, the switching speed of transition between the selected state and non-selected state may be improved.'To summarize, the performance of the memory cell such as power consumption and operation speed may be widely improved.

In the fundamental memory cell construction of FIG.

1, the impedance values of the switched impedance elements connected to the collectors of the transistors T, and T are switched between the non-selected state and selected state, thereby widely improving the memory cell performance compared to the prior art. FIG. 3 shows another memory cell, in which a coupling impedance element Z is provided between the collectors of the transistors T, and T for the purpose of preventing saturation of the transistors and reducing the amplitude of the address pulse. The impedance of the coupling impedance element 2 may be either fixed or variable.

FIG. 4 shows a further modified memory cell, in which Schottky barrier diodes D and D are connected between collector and base of the respective transistors T and T This circuit, though rather difficult to fabricate, is effective in the aspect of preventing the saturation of the transistors T and T It operates under the same principles-as for the circuit of F IG. 1.

FIGLS shows one embodiment of the invention. In the Figure, and in FIGS. 6'to 9, corresponding parts to those in FIG. lare designated by like reference characters. In this circuit, a high value resistor R is connected in parallel with a series circuit of adiode D and a low value resistor R and they constitute the switched impedance element Z in F 10.1, and another high value resistor R is connected in parallel with a series circuit of a diode D and another low value resistor R and they constitute the switched impedance element 2 in FIG. 1. A high value resistor R constitutes the impedance element Z in FIG. 1. A resistor R corresponds to the coupling impedancelelement Z for preventing saturation shown in FIG. 3. It is not an essential element. I a a In this circuit, the collector voltage V emitter volt age V resistances of the resistors R R R and R and diode characteristics of. the diodes D and D are selected such that, in the non-selected state of the memory, the diodes D and D are in the cut-off state or nearly cut off, that is, the voltages across the diodes D and D are below the threshold voltage, and, in the selected state, either one or'both of the diodesD and D carry current, that is, the voltage across either one or both of the diodes D and D is above the threshold FIG. 6 shows another embodiment of the invention. In this circuit, a multi-emitter transistor T replaces the diodes D and D in the preceding embodiment of FIG. 5. An address voltage impressed on a base terminal 3 leading to the transistor T effects the switching between the high value resistor R and low value resistor R for thenon-selected state and selected state. The address voltage applied on the terminal 3, therefore, is such that the transistor T is cut off during the non-selected state and it carries current during the selected state. The collector voltage V impressed on the collector terminal C; may be either fixed or variable. If it is variable, the collector terminal C may be connected to the base terminal 3, and in this case, the collector of the transistor T is connected to a separate d-c power supply, as shown in FIG. 10. The multiemitter transistor T in this embodiment may of course be used in lieu of the diodes D and D shown in FIG. 5.

FIG. 7 shows a further embodiment of the invention. In this circuit, a series circuit of a high value resistor R and a low value resistor R and a diode D in parallel with the resistor R constitute the switched impedance element as the collector load of the transistor T and another series circuit of like components and a diode D in parallel with resistor R constitute the switched impedance element as the collector load of the transistor T The circuit paramenters of this circuit are selected such that, in the non-selected state the diodes D and D are cut off or nearly cut off while in the selected state either one or both of the diodes D and D carry current. Thus, the current in the non-selected state is determined by R R E R (since R R while the current in the selected state is determined by the diodes D and D and the low value resistor R The memory cell of this embodiment, therefore, operates entirely in the same manner as the memory cells of the preceding embodiments.

FIGS. 8 and 9 show still further embodiments of the invention. In the embodiment of FIG. 8, a circuit consisting of parallel resistors R and R and a plurality of diodes D D D connected in a distributed fashion between the parallel resistors constitutes the switched impedance element as the collector load of the transistor T and a-similar circuit consisting of like parallel resistors R and R and a plurality of diodes D D D constitutes the switched impedance element as the collector load of the transistor T The resistors R have one end connected to the collector of the respective transistors T and T and the other end connected to the respective diodes D and D In this circuit, the resistances, diode characteristics and voltage levels applied are selected such that, in the non-selected state of the memory cell most of the diodes D D D and D D D are cut off or nearly cut off, while in the selected state at least one of the diodes nearest to the collector terminal C namely either one or both of the diodes D and D carry current.

In the embodiment of FIG. 9, transistors T T T11, and T T ,T are used in lieu of the diodes D11, D12, D1", and D21, D22, D2" in the prece ing embodiment of FIG. 8. These transistors have their collectors connected to respective terminals 4 and 5, which may be connected either to the terminal C or to a separate constant voltage source.

The switched element, which has diodes as in FIG. 8 or transistors as in FIG. 9 connected in a distributed fashion between two parallel resistors offering different impedances, requires an extremely small area when it is integrated into a semiconductor integrated circuit.

In the preceding embodiments, the common emitter connection between the flip-flop transistors T and T is connected to the emitter bias terminal E through an impedance element 2 whereby a memory cell having switched load impedance elements selectable by a collector driving method may be formed. Where the common emitter connection is connected through the impedance element Z to the emitter bias terminal E it is possible to utilize a semiconductor diffusion region as the impedance element Z In such case, metal film lead between the common emitter connection point and the emitter bias terminal may be reduced or eliminated, thus increasing the degree of integration of the integrated circuit, which is advantageous from the standpoint of economy. I

A memory constructed with the above-stated memory cells having switched load impedance elements selectable by collector driving provides an advantage of low power consumption, which cannot be achieved with memory cells of a similar type but requiring the address pulse impression on the common emitter connection. V g I l FIG. 10 shows a memory cell matrix providing the advantage of low power consumption. The matrix conters AD and AD designate X address lines, characters sists of memory cells M M generally, there are n by m memory cells in a matrix, and only four memory cells are shown in this example. The memory cells in this matrix are a modification of the memory cell of FIG. 6. These memory cells are by no means limitative, but other memory cells may of course be used. Charac- D D D and D 2 designate bit drive lines, and characters J and J designate current sources to provide write or read drive current I The bit drive lines D D D and D are selected by transistors T T T and T having their .base connected to respective Y address terminalsY and Y on which Y address select voltage is impressed. The memory cells M M M and M are selected when drive voltage appears on the corresponding one of the X address lines AD and Ad and on the corresponding one of the T address terminals Y and Y The reference level of the Y address select voltage, which is impressed on the base terminals Y and Y for the respective pairs of Y address transistors T T T T is determined by thevoltage V applied to the base of a two-emitter transistor T having one emitter connected to the emitter of the transistors T and T and the other emitter connected to the emitter of the transistors T and T The two emitters of the transistor T are also connected to the respective emitters of transistors T and T The transistors T and T serve to prevent the current I from the current source J or J from flowing into one of the selected bit drive lines in pair in dependence upon whether the base voltages V and V on the transistors T and T4 are higher or lower than the T address select voltage'impressed on the Y address terminal T or T Transistors T and T constitute a sense amplifier, which reads out the memory content of the selected memory cell in terms of its collector output voltages V and V If voltage of high level prevails at terminal Y, and voltage of low level at terminal Y the bit drive lines D and D in pair are selected, while the transistors T and'T are non-conductive. At this time, if voltage of high level appears on the X address line AD,, the second emitters in the memory cell Mg remain nonconductive. By virture of the emitter resistor R in each memory cell in the matrix of FIG. 10, always one of the first emitters in pair carries current. Thus, even if the second emitters in a selected memory cell remain non-conductive, the memorycontent in the selected memory cell will not be destroyed. In the conventional memory cell of the emitter address drive type, if both the second emitters remain non-conductive when it is selected the memory content would be destroyed. According to the invention, by vir-ture of the emitter impedance Z it is not necessary to provide the current sources J and J as shown in FIG. 10 for each column in the matrix. Thus, it will be seen that the circuitry associated to the memory cell matrix may be simplified and the power consumption of the memory may be reduced.

For reducing the selected state collector impedance of a memory cell consisting of two multi-emitter transistors, it can be considered to connect diodes between the collector drive voltage terminal and the respective collectors in the cell. By so doing, the'saturation of the flip-flop transistors may beprevented. In such case, however, if both the diodes connected to the respective collectors become conductive, the collector potentials on both sides of the flip-flop becomes substantially equal, so thatthe memory content will apparently be destroyed. According to the invention, the impedance switching diodesor transistors in the memory cell are arranged such thatboth the collector load impedances assume low values other than zero when both the diodes or transistors are triggered upon selection of the cell; for instance, alow value resistor is connected in series with the diode or the emitter of the transistor in the collector load. This feature enables increasing the current ratio l /l more than ten times, as largeas thatheretofore achievable.

Although .in theforegoing embodiments suitable.

switchable .for the nonselected state and selected state,

so that it is possible to extremely reduce power consumption of the memory cell during the non-selected state and increase the operating speed by increasing the read-out current during the selected state. Thus, a semiconductor memoryorg anized from these memory cells can provide outstandinglyimproved performance.

The foregoing description has indicated that the collector bias voltage V is merely switched from a low level to a high level and vice versa but this may also include use of anaddress signal having a high level and a low level incorporated or superimposed on the constant level collector bias voltage.

What is claimed is:

1. In a semiconductor memory comprising:

a. at least one memory cell'including l. a pair of double-emitter transistors each having a collector, a base and first and second emitters, the collector of each one of said pair of transistors being connected to the base of the other, respectively, and the first emitters of said pair of transistors being connected together,

2. an emitter impedance element connected at one end thereof to the commonly connected first emitters of said pair of transistors, and

3. a pair of relatively high-valued impedance elements eachconnected at one end thereof to the v ments, respectively.

6. An improvement in a semiconductor memory ac- 8 collector of a respective one of the pair of transistors, respectively; I

b. a pair of digit lines for said memory cell connected to the second emitters of said pair of transistors, respectively; l

c. a source of a constant emitter bias voltage connected to the other end of said emitter impedanc element;

d. an address line for said memory cell; and

e. a source of an address voltage connected to said address line, said address voltage presenting a high or a low'level when the corresponding memory cell is to be selected or non-selected, respectively;

the improvement which comprises:

a switching transistor having a collector, a base and double-emitters; and

a pair of relatively low-valued impedance elements each having a relatively low-valued impedance with respect to that of said high-valued impedance elements and connected between one of the double-emitters of said switching transistor and the collector of one of said pair of transistors, respectively;' V J a the base of said switching transistor being connected to said address line, said address voltage of the high or'the low level rendering said switching transistor conductive or non-conductive, respectively, so that the low-valued impedance elements are loaded in the collector circuits of said pair of transistors concurrently when the address voltage presents the high level. 1 r 2. The combination accordingto-claim l,'wherein said high-valued impedance elementsare resistors having respectively a relatively highevalued resistance, and said low-valued impedance elements are resistors having respectively a relatively low-valued resistance with respect to that of said high-valued impedance elements.

3. The combination according to claim 1 which further comprises a source of a constant collector bias voltage connected to the collector of said switching transistor.

4. The combination according to claim'3 which further comprises means for connecting the source of the constant collector bias voltage to'the other ends of the high-valued impedance elements, respectively.

5. The combination according to claim 3 which further comprises means for connecting said address line to the other ends of said high-valued impedance elecording to claim 1 which further comprises a coupling impedance element connected between the collectors of the pair of transistors for preventing said pair of transistors from saturation.

7. The improvement according to claim 6, wherein said coupling impedance element comprises a pair of Schottky barrier diodes connected in parallel with and in opposite conductive direction to each other.

8. A bipolar semiconductor memory cell comprising:

a. a pair of double-emitter transistors each having collector and base electrodes and first and second emitter electrodes, the collector and base elecelectrodes of said pair of transistors being connected together so that said pair of transistors attain bistable operation, the second emitter electrodes of said pair of transistors being connected with a pair of digit lines, respectively;

b an emitter resistor connected at one end thereof with the commonly connected first emitter electrodes and at the other end thereof with a terminal at which a constant potential is applied;

c. a pair of relatively high-valued resistance elements connected respectively with the collector electrodes of said pair of transistors,

d. a double-emitter switching transistor having collector, base and two emitter electrodes;

e. a pair of relatively low-valued resistance elements connected between the emitter electrodes of said switching transistor and the collector electrodes of said pair of transistors, respectively;

f. address means for supplying to the base electrode of said switching transistor an address voltage having active and inactive states when the cell is to be selected and non-selected, respectively, the potentials of the address voltage in the active and inactive states being so selected as to render the switching transistor into on and off states of conduction, respectively,

g. a first potential source connected with the other ends of said high-valued resistance elements; and h. a second potential source connected with the collector electrode of said switching transistor, so that the collector electrodes of said pair of transistors are supplied with a collector operation potential through the high-valued resistance elements when the cell is non-selected, or through the series circuits of the switching transistor and the low-valued resistance element, which series circuits are shunting the high-valued resistance elements, when the cell is selected. 

1. In a semiconductor memory comprising: a. at lEast one memory cell including
 1. a pair of double-emitter transistors each having a collector, a base and first and second emitters, the collector of each one of said pair of transistors being connected to the base of the other, respectively, and the first emitters of said pair of transistors being connected together,
 2. an emitter impedance element connected at one end thereof to the commonly connected first emitters of said pair of transistors, and
 3. a pair of relatively high-valued impedance elements each connected at one end thereof to the collector of a respective one of the pair of transistors, respectively; b. a pair of digit lines for said memory cell connected to the second emitters of said pair of transistors, respectively; c. a source of a constant emitter bias voltage connected to the other end of said emitter impedance element; d. an address line for said memory cell; and e. a source of an address voltage connected to said address line, said address voltage presenting a high or a low level when the corresponding memory cell is to be selected or nonselected, respectively; the improvement which comprises: a switching transistor having a collector, a base and doubleemitters; and a pair of relatively low-valued impedance elements each having a relatively low-valued impedance with respect to that of said high-valued impedance elements and connected between one of the double-emitters of said switching transistor and the collector of one of said pair of transistors, respectively; the base of said switching transistor being connected to said address line, said address voltage of the high or the low level rendering said switching transistor conductive or nonconductive, respectively, so that the low-valued impedance elements are loaded in the collector circuits of said pair of transistors concurrently when the address voltage presents the high level.
 2. an emitter impedance element connected at one end thereof to the commonly connected first emitters of said pair of transistors, and
 2. The combination according to claim 1, wherein said high-valued impedance elements are resistors having respectively a relatively high-valued resistance, and said low-valued impedance elements are resistors having respectively a relatively low-valued resistance with respect to that of said high-valued impedance elements.
 3. The combination according to claim 1 which further comprises a source of a constant collector bias voltage connected to the collector of said switching transistor.
 3. a pair of relatively high-valued impedance elements each connected at one end thereof to the collector of a respective one of the pair of transistors, respectively; b. a pair of digit lines for said memory cell connected to the second emitters of said pair of transistors, respectively; c. a source of a constant emitter bias voltage connected to the other end of said emitter impedance element; d. an address line for said memory cell; and e. a source of an address voltage connected to said address line, said address voltage presenting a high or a low level when the corresponding memory cell is to be selected or non-selected, respectively; the improvement which comprises: a switching transistor having a collector, a base and double-emitters; and a pair of relatively low-valued impedance elements each having a relatively low-valued impedance with respect to that of said high-valued impedance elements and connected between one of the double-emitters of said switching transistor and the collector of one of said pair of transistors, respectively; the base of said switching transistor being connected to said address line, said address voltage of the high or the low level rendering said switching transistor conductive or non-conductive, respectively, so that the low-valued impedance elements are loaded in the collector circuits of said pair of transistors concurrently when the address voltage presents the high level.
 4. The combination according to claim 3 which further comprises means for connecting the source of the constant collector bias voltage to the other ends of the high-valued impedance elements, respectively.
 5. The combination according to claim 3 which further comprises means for connecting said address line to the other ends of said high-valued impedance elements, respectively.
 6. An improvement in a semiconductor memory according to claim 1 which further comprises a coupling impedance element connected between the collectors of the pair of transistors for preventing said pair of transistors from saturation.
 7. The improvement according to claim 6, wherein said coupling impedance element comprises a pair of Schottky barrier diodes connected in parallel with and in opposite conductive direction to each other.
 8. A bipolar semiconductor memory cell comprising: a. a pair of double-emitter transistors each having collector and base electrodes and first and second emitter electrodes, the collector and base electrodes of each of said pair of transistors being directly cross-coupled to the base and collector electrodes of the other, respectively, the first emitter electrodes of said pair of transistors being connected together so that said pair of transistors attain bistable operation, the second emitter electrodes of said pair of transistors being connected with a pair of digit lines, respectively; b. an emitter resistor connected at one end thereof with the commonly connected first emitter electrodes and at the other end thereof with a terminal aT which a constant potential is applied; c. a pair of relatively high-valued resistance elements connected respectively with the collector electrodes of said pair of transistors, d. a double-emitter switching transistor having collector, base and two emitter electrodes; e. a pair of relatively low-valued resistance elements connected between the emitter electrodes of said switching transistor and the collector electrodes of said pair of transistors, respectively; f. address means for supplying to the base electrode of said switching transistor an address voltage having active and inactive states when the cell is to be selected and non-selected, respectively, the potentials of the address voltage in the active and inactive states being so selected as to render the switching transistor into on and off states of conduction, respectively, g. a first potential source connected with the other ends of said high-valued resistance elements; and h. a second potential source connected with the collector electrode of said switching transistor, so that the collector electrodes of said pair of transistors are supplied with a collector operation potential through the high-valued resistance elements when the cell is non-selected, or through the series circuits of the switching transistor and the low-valued resistance element, which series circuits are shunting the high-valued resistance elements, when the cell is selected. 